The invention generally relates to electronic signal synchronization and, more particularly, producing a timing signal for use by a device for clocking at least one process executed by the device.
Network devices commonly communicate by synchronizing their inter-device data transmissions to a widely recognized standard clock signal known as the xe2x80x9cstratum clock.xe2x80x9d As known by those skilled in the art, the stratum clock is a precise clock signal that is a multiple of eight kilohertz. Accordingly, it is important for such network devices to be synchronized to the stratum clock when transmitting data to other such network devices. Specifically, among other reasons, transmitted data can be lost and/or corrupted if such network devices receive data that is not synchronized to the stratum clock.
To synchronize with the stratum clock, network devices first typically derive an internal clock signal that is synchronized to the stratum clock. Such internal clock signal generally is synchronized to an incoming signal from another network device that also is synchronized to the stratum clock. Once generated, the internal signal typically may be utilized to clock data that is to be transmitted across a network to another similarly synchronized network device. For example, the internal signal may be scaled, but still synchronized with the stratum clock, to facilitate processes that generate data transmissions to another similarly synchronized network device.
The internal signal may be derived by a number of methods. For example, one commonly utilized method first determines the actual frequency of the incoming signal, and then utilizes divide down hardware and/or software to obtain a specific timing signal (e.g., an eight kilohertz signal). Undesirably, in addition to the divide down hardware and/or software, the hardware and/or software for determining the actual frequency requires a relatively significant overhead cost.
In accordance with one aspect of the invention, an apparatus and method of producing a clock signal synchronize such signal to a periodic incoming signal. Each period in the incoming signal has a reference point that is utilized to produce the clock signal. To that end, the reference point of a first period of the incoming signal first is detected. The clock signal then is set to a first logic level upon detection of the reference point. Moreover, also upon detection of the reference point, a count is begun for a predetermined time interval. The clock signal is latched to a second logic level upon expiration of a portion of the predetermined time interval. The first logic level is different from the second logic level.
In illustrative embodiments, the reference point of a second period is detected, and the clock signal then substantially immediately is set to the first logic level. The first and second periods may be consecutive, or separated by one or more periods. The count then is begun again for the predetermined time interval again upon detection of the reference point of the second period. The clock signal subsequently is latched to the second logic level upon expiration of about half of the predetermined time interval.
The clock signal may be multiplied by a scalar to conform with an internal oscillator. In addition, the reference point may be a transition from the second logic level to the first logic level. In some embodiments, the clock signal is utilized by a first network device for clocking one of its internal processes. The first network device also may be coupled with a second network device having a second network device signal for clocking one of its internal processes that receives data transmitted to it from the first network device. The clock signal thus is synchronized with the second network device signal.
The incoming signal may have a frequency that is a first multiple of a given frequency. In addition, the clock signal may have a frequency that is a second multiple of the given frequency. In some embodiments, the predetermined time interval is inversely proportional to the given frequency. In yet other embodiments, the portion of the preselected time interval is about half of the preselected time interval.
In accordance with another aspect of the invention, a signal generator for producing a clock signal that is synchronous with a periodic incoming signal (i.e., the incoming signal noted above) includes a logic element that receives the incoming signal, and a timer that is capable of transmitting an enable signal to the logic element. The logic element has an output for transmitting the produced clock signal, and an enable input for receiving the enable signal from the timer. When enabled, the logic element is capable of detecting the reference point in each of a set of periods of the incoming signal. The timer is capable of transmitting the enable signal to the logic element once during a preselected time interval after a previous enable signal is set to logical zero. The logic element sets the clock signal to a first logic level each time the reference point is detected (while it is enabled). Conversely, after the clock signal is set to the first logic level, the logic element sets the clock signal to a second logic level upon expiration of about half of the preselected time interval.